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A static test compaction technique for combinational circuits based on independent fault clustering., and . ICECS, page 1316-1319. IEEE, (2003)A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance., , and . DAC, page 625-631. ACM Press, (1998)On efficient extraction of partially specified test sets for synchronous sequential circuits., and . ISCAS (5), page 545-548. IEEE, (2003)An Efficient Test Relaxation Technique for Synchronous Sequential Circuits., and . VTS, page 179-185. IEEE Computer Society, (2003)Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression., and . ICECS, page 449-452. IEEE, (2002)A hybrid test compression technique for efficient testing of systems-on-a-chip.. ICECS, page 599-602. IEEE, (2003)General iterative heuristics for VLSI multiobjective partitioning., , and . ISCAS (5), page 497-500. IEEE, (2003)A scheme of test data compression based on coding of even bits marking and selective output inversion., , , , and . Comput. Electr. Eng., 36 (5): 969-977 (2010)Delay-fault testability preservation of the concurrent decomposition and factorization transformations., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (5): 582-590 (1995)Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning., , and . ISCAS (5), page 457-460. IEEE, (2003)