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A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.

T. Li, N. Jing, J. Jiang, Q. Wang, Z. Mao, and Y. Chen. ACM Trans. Design Autom. Electr. Syst., 27 (6): 57:1-57:22 (2022)

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Jianfei Kralle

Jianfei Wang

Jianfei Wei

Jianzhong Jiang

Andong Jiang

Other publications of authors with the same name

Analog-to-digital converter based on single-electron tunneling transistors.C. Hu, S. Cotofana, J. Jiang, and Q. Cai. IEEE Trans. Very Large Scale Integr. Syst., 12 (11): 1209-1213 (2004)Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.Y. Chen, Z. Zhao, J. Jiang, G. He, Z. Mao, and W. Sheng. DATE, page 124-129. IEEE, (2021)Design of a high voltage stimulator chip for a stroke rehabilitation system.L. Zeng, X. Yi, S. Lu, Y. Lou, J. Jiang, H. Qu, N. Lan, and G. Wang. EMBC, page 834-837. IEEE, (2013)A Hierarchical Communication Algorithm for Distributed Deep Learning Training.J. Zhang, S. Cheng, F. Dong, K. Chen, Y. Qiao, Z. Mao, and J. Jiang. MWSCAS, page 526-530. IEEE, (2023)Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing.Z. Yan, G. He, Y. Ren, W. He, J. Jiang, and Z. Mao. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (11): 2706-2717 (2015)A CPU-FPGA Based Heterogeneous Accelerator for RepVGG.Y. Guo, M. Jiang, F. Dong, K. Yu, K. Chen, W. Qu, and J. Jiang. ASICON, page 1-4. IEEE, (2021)Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.T. Hong, N. Guan, C. Yin, Q. Wang, J. Jiang, J. Jin, G. He, and N. Jing. ISCAS, page 1-5. IEEE, (2020)Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture.L. Chen, J. Jiang, Q. Wang, Z. Mao, and N. Jing. ASPDAC, page 460-465. IEEE, (2024)Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.P. Liu, Z. Zhang, C. Yin, L. Chen, J. Jiang, Q. Wang, Z. Mao, and N. Jing. FPL, page 116-122. IEEE, (2023)A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.Z. Zhang, J. Jiang, W. Sheng, Q. Wang, Z. Mao, and N. Jing. BigDataSecurity, page 180-185. IEEE, (2021)

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Disambiguation of "Jiang, Jianfei"

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A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.

Please choose a person to relate this publication to

Jianfei Kralle

Jianfei Wang

Jianfei Wei

Jianzhong Jiang

Andong Jiang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jiang, Jianfei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.

Please choose a person to relate this publication to

Jianfei Kralle

Jianfei Wang

Jianfei Wei

Jianzhong Jiang

Andong Jiang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.