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A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.

T. Li, N. Jing, J. Jiang, Q. Wang, Z. Mao, and Y. Chen. ACM Trans. Design Autom. Electr. Syst., 27 (6): 57:1-57:22 (2022)

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Naifeng Liu

Yuanyuan Jing

Guangmei Jing

Hao Jing

Duohui Jing

Other publications of authors with the same name

Contention and energy aware mapping for real-time applications on Network-on-Chip.B. Ge, N. Jing, W. He, and Z. Mao. ISOCC, page 72-76. IEEE, (2012)Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.N. Jing, S. Jiang, S. Chen, J. Zhang, L. Jiang, C. Li, and X. Liang. IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 520-533 (2017)Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images.S. Zhang, G. He, H. Chen, N. Jing, and Q. Wang. IEEE Geosci. Remote. Sens. Lett., 16 (6): 864-868 (2019)A general statistical estimation for application mapping in Network-on-Chip.N. Jing, W. He, and Z. Mao. VLSI-SoC, page 172-175. IEEE, (2011)Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array.N. Jing, W. He, and Z. Mao. SoCC, page 260-265. IEEE, (2010)Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.N. Jing, J. Zhou, J. Jiang, X. Chen, W. He, and Z. Mao. ICCAD, page 764-769. IEEE, (2015)On Quality Trade-off Control for Approximate Computing Using Iterative Training.C. Xu, X. Wu, W. Yin, Q. Xu, N. Jing, X. Liang, and L. Jiang. DAC, page 52:1-52:6. ACM, (2017)IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.Z. Feng, N. Jing, G. Chen, Y. Hu, and L. He. FPL, page 482-485. IEEE Computer Society, (2011)CMC: Video Transformer Acceleration via CODEC Assisted Matrix Condensing.Z. Song, C. Qi, F. Liu, N. Jing, and X. Liang. ASPLOS (2), page 201-215. ACM, (2024)SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration.C. Yin, J. Jiang, Q. Wang, Z. Mao, and N. Jing. ASPDAC, page 225-230. IEEE, (2024)

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Disambiguation of "Jing, Naifeng"

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A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.

Please choose a person to relate this publication to

Naifeng Liu

Yuanyuan Jing

Guangmei Jing

Hao Jing

Duohui Jing

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jing, Naifeng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.

Please choose a person to relate this publication to

Naifeng Liu

Yuanyuan Jing

Guangmei Jing

Hao Jing

Duohui Jing

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.