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Disambiguation of "Wen, Xiaoqing"

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STAHL: A Novel Scan-Test-Aware Hardened Latch Design.

, , , , and . ETS, page 1-6. IEEE, (2019)

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Xiaoqing Pan

Xiaoqing Liu

Xiaoqing Li

Xiaoqing Shen

Xiaoqing Jin

 

Other publications of authors with the same name

Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , and . ITC-Asia, page 139-144. IEEE, (2019)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 38-49 (2016)Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test., , and . PRDC, page 124-129. IEEE, (2019)Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications., , , , , , , and . ATS, page 43-48. IEEE, (2019)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , and . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing., , , , and . IEICE Trans. Inf. Syst., 94-D (4): 833-840 (2011)Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (3): 499-512 (2016)