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High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.

, , , , , , , and . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)

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Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test., , and . PRDC, page 124-129. IEEE, (2019)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , and . ITC-Asia, page 139-144. IEEE, (2019)Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications., , , , , , , and . ATS, page 43-48. IEEE, (2019)Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications., , , , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 58 (1): 517-529 (2022)Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications., , , , , , and . Microelectron. J., (September 2023)Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling., , and . MCSoC, page 501-507. IEEE, (2023)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 38-49 (2016)Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)