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Physical-design-friendly hierarchical logic built-in self-test - A case study.

, , , , , , , , , , и . ISQED, стр. 1-6. IEEE, (2012)

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Jinglan Wu

Recovery of citric acid from fermentation broth using simulated moving bed technology: = Reinigung von Zitronensäure aus Fermentationslösung durch kontinuierliche Chromatographie. Uni Erlangen-Nürnberg, (2009)

Zongmin Wu

Dagang Wu

Weijia Wu

Hongzhong Wu

 

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A Sequential Circuit Test Generation System., и . ITC, стр. 57-61. IEEE Computer Society, (1985)At-Speed Logic BIST for IP Cores., , , , , , , , и . DATE, стр. 860-861. IEEE Computer Society, (2005)At-Speed Logic BIST Architecture for Multi-Clock Designs., , , , и . ICCD, стр. 475-478. IEEE Computer Society, (2005)A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing., , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2006)Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains., , , , , , , , , и 2 other автор(ы). DFT, стр. 358-366. IEEE Computer Society, (2010)CSER: BISER-based concurrent soft-error resilience., , , , , и . VTS, стр. 153-158. IEEE Computer Society, (2010)Analysis of Resistive Bridging Defects in a Synchronizer., , , и . Asian Test Symposium, стр. 443-449. IEEE Computer Society, (2009)Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs., , , , , , , и . DFT, стр. 331-339. IEEE Computer Society, (2010)On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs., , , , , , , , , и . DFT, стр. 143-151. IEEE Computer Society, (2008)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , и 2 other автор(ы). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)