( en | de | ru )

 

Disambiguation of "Luu, Jason"

Author of the publication

copydeleteadd this publication to your clipboard
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect.

, , and . FPGA, page 227-236. ACM, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ian Jason

Luu Quang Minh

Luu Dat Thuyet

Luu Duan

Keurcien Luu

 

Other publications of authors with the same name

Hybrid LUT/Multiplexer FPGA Logic Architectures., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1280-1292 (2016)VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling., , , , , , and . FPGA, page 133-142. ACM, (2009)Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect., , and . FPGA, page 227-236. ACM, (2011)The VTR project: architecture and CAD for FPGAs from verilog to routing., , , , , , , , and . FPGA, page 77-86. ACM, (2012)FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy., , , , , and . FCCM, page 157-164. IEEE Computer Society, (2009)VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling., , , , , , , , , and 5 other author(s). ACM Trans. Reconfigurable Technol. Syst., 13 (2): 9:1-9:55 (2020)Optimizing FPGA Logic Block Architectures for Arithmetic., , , , , , , , , and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1378-1391 (2020)From Quartus to VPR: Converting HDL to BLIF with the Titan flow., , , , and . FPL, page 1. IEEE, (2013)On Hard Adders and Carry Chains in FPGAs., , , , , , , , , and . FCCM, page 52-59. IEEE Computer Society, (2014)Towards interconnect-adaptive packing for FPGAs., , and . FPGA, page 21-30. ACM, (2014)