Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Pre- and post-BD electrical conduction of stressed HfO2/SiO2 MOS gate stacks observed at the nanoscale., , , and . Microelectron. Reliab., 45 (9-11): 1390-1393 (2005)Reliability simulation for analog ICs: Goals, solutions, and challenges., , , , , , , and . Integr., (2016)Investigation of Conductivity Changes in Memristors under Massive Pulsed Characterization., , , , and . DCIS, page 1-4. IEEE, (2018)Effect of oxide breakdown on RS latches., , , and . Microelectron. Reliab., 47 (4-5): 581-584 (2007)Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells., , , , , , , and . SMACD, page 1-4. IEEE, (2017)Threshold voltage and on-current Variability related to interface traps spatial distribution., , , , , , , , and . ESSDERC, page 230-233. IEEE, (2015)Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies., , , , , , , , and . DATE, page 1322-1327. ACM, (2008)CMOS Characterization and Compact Modelling for Circuit Reliability Simulation., , , , , , and . IOLTS, page 139-142. IEEE, (2018)A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation., , , , , , , , and . SMACD, page 53-56. IEEE, (2018)Automated Massive RTN Characterization Using a Transistor Array Chip., , , , , , , , and . SMACD, page 29-32. IEEE, (2018)