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Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM.

, , , , and . ISOCC, page 479-482. IEEE, (2012)

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Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_MIN$ Improvement and Energy Saving., , , , , , , and . IEEE J. Solid State Circuits, 54 (3): 896-906 (2019)Power-Gated 9T SRAM Cell for Low-Energy Operation., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1183-1187 (2017)Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter., , , , and . ICECS, page 400-403. IEEE, (2015)Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead., and . IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1728-1738 (2022)Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM., , , , and . ISOCC, page 479-482. IEEE, (2012)Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits., , , , and . ICECS, page 833-836. IEEE, (2012)A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology., , , , , , , , , and 9 other author(s). ISSCC, page 392-394. IEEE, (2019)Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1059-1063 (2016)Pseudo NMOS based sense amplifier for high speed single-ended SRAM., , , , and . ICECS, page 331-334. IEEE, (2014)Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 4949-4961 (December 2023)