Autor der Publikation

Bitte wählen Sie eine Person um die Publikation zuzuordnen

Um zwischen Personen mit demselben Namen zu unterscheiden, wird der akademische Grad und der Titel einer wichtigen Publikation angezeigt. Zudem lassen sich über den Button neben dem Namen einige der Person bereits zugeordnete Publikationen anzeigen.

 

Weitere Publikationen von Autoren mit dem selben Namen

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , und 12 andere Autor(en). ISSCC, Seite 388-390. IEEE, (2019)5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel., , , , , , , , , und 3 andere Autor(en). ISSCC, Seite 110-112. IEEE, (2020)13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices., , , , , , , , , und 2 andere Autor(en). ISSCC, Seite 224-226. IEEE, (2020)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse., , , , , , , , , und 1 andere Autor(en). ISSCC, Seite 234-236. IEEE, (2020)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , und 1 andere Autor(en). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements., , , , , und . IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache., , , , , und . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (4): 858-868 (2017)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , und . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (November 2023)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 52-64 (Januar 2024)