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Disambiguation of "Tawada, Masashi"

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Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design.

, , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2020)

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Masashi Urabe

Masashi Egawa

Masashi Haneda

Yōko Tawada

 

Other publications of authors with the same name

Error Correction Coding of Stochastic Numbers Using BER Measurement., , , and . IOLTS, page 243-246. IEEE, (2019)An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines., , , and . VLSI-DAT, page 1-4. IEEE, (2021)A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines., , and . ICCE, page 1-6. IEEE, (2020)Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories., , , and . ICCAD, page 682-689. IEEE, (2015)A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (12): 2398-2411 (2016)A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (6): 1283-1292 (2013)An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits., , , and . IOLTS, page 53-56. IEEE, (2018)FPGA-based Heterogeneous Solver for Three-Dimensional Routing., , , , , and . ASP-DAC, page 11-12. IEEE, (2020)A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (7): 1045-1052 (2018)A bit-write reduction method based on error-correcting codes for non-volatile memories., , , and . ASP-DAC, page 496-501. IEEE, (2015)