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A Task-Centric Memory Model for Scalable Accelerator Architectures., , , , and . IEEE Micro, 30 (1): 29-39 (2010)Emµcode: Masking hard faults in complex functional units., , and . DSN, page 458-467. IEEE Computer Society, (2009)Fetch-Criticality Reduction through Control Independence., , , and . ISCA, page 13-24. IEEE Computer Society, (2008)LoGPC: Modeling Network Contention in Message-Passing Programs., and . IEEE Trans. Parallel Distributed Syst., 12 (4): 404-415 (2001)SUDS: automatic parallelization for raw processors.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2003)ndltd.org (oai:dspace.mit.edu:1721.1/17591).SPARTAN: A software tool for Parallelization Bottleneck Analysis., and . IWMSE@ICSE, page 56-63. IEEE Computer Society, (2009)A Task-Centric Memory Model for Scalable Accelerator Architectures., , , , and . PACT, page 77-87. IEEE Computer Society, (2009)A Hybrid Shared Memory/Message Passing Parallel Machine., and . ICPP (1), page 232-236. CRC Press, (1993)Branch-mispredict level parallelism (BLP) for control independence., , , , and . HPCA, page 62-73. IEEE Computer Society, (2008)PaCo: Probability-based path confidence prediction., , , and . HPCA, page 50-61. IEEE Computer Society, (2008)