Author of the publication

Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics.

, , , and . ISOCC, page 243-244. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Soft error tolerant latch design with low cost for nanoelectronic systems., and . ISCAS, page 1572-1575. IEEE, (2012)Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length., and . ISCAS, page 998-1001. IEEE, (2012)Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics., , , and . ISOCC, page 243-244. IEEE, (2016)Artificial neural network implementation in FPGA: A case study., , and . ISOCC, page 297-298. IEEE, (2016)Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously., , and . ISQED, page 74-79. IEEE, (2011)Power dissipation and area comparison of 512-bit and 1024-bit key AES., , , and . Comput. Math. Appl., 65 (9): 1378-1383 (2013)System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles., , , , , and . ISOCC, page 151-155. IEEE, (2018)Hardware-efficient parallel FIR digital filter structures for symmetric convolutions., and . ISCAS, page 2301-2304. IEEE, (2011)Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology., , and . EIT, page 405-410. IEEE, (2009)Prototyping circuit design for Dielectric Electroactive Polymers energy harvesting., , , , and . ISOCC, page 450-453. IEEE, (2011)