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Disambiguation of "Wang, Chua-Chin"

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An 80MHz PLL with 72.7ps peak-to-peak jitter.

, , , and . Microelectron. J., 38 (6-7): 716-721 (2007)

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Wang- Chin Kim

Chin-hsien Wang

Stephanie Chua

Siewteen Chua

Modesto Chua

 

Other publications of authors with the same name

An SRAM design using dual threshold voltage transistors and low-power quenchers., , and . IEEE J. Solid State Circuits, 38 (10): 1712-1720 (2003)Design of an Inter-plane Circuit for Clocked PLAs., , , and . VLSI Design, 14 (4): 373-381 (2002)A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2172-2185 (2021)2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation., , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (7): 812-816 (2017)A Self-Disabled Sensing Technique for Content-Addressable Memories., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (1): 31-35 (2010)A High-Precision CMOS Temperature Sensor with Thermistor Linear Calibration in the (-5 °C, 120 °C) Temperature Range., , and . Sensors, 18 (7): 2165 (2018)A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (5): 1069-1076 (2007)One-Time-Implantable Spinal Cord Stimulation System Prototype., , , and . IEEE Trans. Biomed. Circuits Syst., 5 (5): 490-498 (2011)Fuzzy data recall using polynomial bidirectional hetero-correlator., and . SMC, page 1940-1945. IEEE, (1998)A Signed Array Multiplier with Bypassing Logic., , , and . J. Signal Process. Syst., 66 (2): 87-92 (2012)