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A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

B. Leibowitz, J. Kizer, H. Lee, F. Chen, A. Ho, M. Jeeradit, A. Bansal, T. Greer, S. Li, R. Farjad-Rad, W. Stonecypher, Y. Frans, B. Daly, F. Heaton, B. Garlepp, C. Werner, N. Nguyen, V. Stojanovic, and J. Zerbe. ISSCC, page 228-599. IEEE, (2007)

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Christoph Garlepp

Bruno W Neu

Paul W Bruno

Bruno W Nikles

Ewald Garlepp

Other publications of authors with the same name

A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter.M. Perrott, Y. Huang, R. Baird, B. Garlepp, L. Zhang, and J. Hein. ISSCC, page 1276-1285. IEEE, (2006)A new technique for characterization of digital-to-analog converters in high-speed systems.J. Savoj, A. Abbasfar, A. Amirkhany, B. Garlepp, and M. Horowitz. DATE, page 433-438. EDA Consortium, San Jose, CA, USA, (2007)1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus.J. Zerbe, P. Chau, C. Werner, T. Thrush, H. Liaw, B. Garlepp, and K. Donnelly. IEEE J. Solid State Circuits, 36 (5): 752-760 (2001)A portable digital DLL for high-speed CMOS interface circuits.B. Garlepp, K. Donnelly, J. Kim, P. Chau, J. Zerbe, C. Huang, C. Tran, C. Portmann, D. Stark, Y. Chan and 2 other author(s). IEEE J. Solid State Circuits, 34 (5): 632-644 (1999)A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator.M. Perrott, S. Pamarti, E. Hoffman, F. Lee, S. Mukherjee, C. Lee, V. Tsinker, S. Perumal, B. Soto, N. Arumugam and 1 other author(s). ISSCC, page 244-245. IEEE, (2010)A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator.M. Perrott, S. Pamarti, E. Hoffman, F. Lee, S. Mukherjee, C. Lee, V. Tsinker, S. Perumal, B. Soto, N. Arumugam and 1 other author(s). IEEE J. Solid State Circuits, 45 (12): 2566-2581 (2010)A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation.D. Wei, Y. Huang, B. Garlepp, and J. Hein. ISSCC, page 884-893. IEEE, (2006)

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Disambiguation of "Garlepp, Bruno W."

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A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

Please choose a person to relate this publication to

Christoph Garlepp

Bruno W Neu

Paul W Bruno

Bruno W Nikles

Ewald Garlepp

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Garlepp, Bruno W."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

Please choose a person to relate this publication to

Christoph Garlepp

Bruno W Neu

Paul W Bruno

Bruno W Nikles

Ewald Garlepp

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.