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Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee., , и . ISSCC, стр. 124-125. IEEE, (2021)ADC-based Wireline Transceiver.. CICC, стр. 1-89. IEEE, (2019)Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 55 (4): 1086-1095 (2020)A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET., , , , , , , , , и 6 other автор(ы). IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 45 (4): 889-898 (2010)A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 204-205. IEEE, (2023)A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET., , , , , , , , , и 5 other автор(ы). VLSI Circuits, стр. 47-48. IEEE, (2018)A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET., , , , , , , , , и . VLSI Circuits, стр. 190-. IEEE, (2019)A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 108-110. IEEE, (2018)3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)