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A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

B. Leibowitz, J. Kizer, H. Lee, F. Chen, A. Ho, M. Jeeradit, A. Bansal, T. Greer, S. Li, R. Farjad-Rad, W. Stonecypher, Y. Frans, B. Daly, F. Heaton, B. Garlepp, C. Werner, N. Nguyen, V. Stojanovic, and J. Zerbe. ISSCC, page 228-599. IEEE, (2007)

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Yohan Shim

Yohan Seo

Yohan Lejosne

Fekadu Yohannes

Indra Yohannes

Other publications of authors with the same name

Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET.M. Raj, Y. Frans, P. Chiang, S. Ambatipudi, D. Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, J. Grayson, M. Epitaux and 1 other author(s). IEEE J. Solid State Circuits, 55 (4): 1086-1095 (2020)ADC-based Wireline Transceiver.Y. Frans. CICC, page 1-89. IEEE, (2019)Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee.Y. Frans, P. Yue, and T. Toifl. ISSCC, page 124-125. IEEE, (2021)3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.P. Upadhyaya, J. Savoj, F. An, A. Bekele, A. Jose, B. Xu, Z. Wu, D. Turker, H. Aslanzadeh, H. Hedayati and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.B. Leibowitz, R. Palmer, J. Poulton, Y. Frans, S. Li, J. Wilson, M. Bucher, A. Fuller, J. Eyles, M. Aleksic and 2 other author(s). IEEE J. Solid State Circuits, 45 (4): 889-898 (2010)A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.M. Raj, Y. Frans, S. Ambatipudi, D. Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, J. Grayson, M. Epitaux, and K. Chang. VLSI Circuits, page 190-. IEEE, (2019)A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.P. Upadhyaya, C. Poon, S. Lim, J. Cho, A. Roldan, W. Zhang, J. Namkoong, T. Pham, B. Xu, W. Lin and 6 other author(s). IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.P. Upadhyaya, C. Poon, S. Lim, J. Cho, A. Roldan, W. Zhang, J. Namkoong, T. Pham, B. Xu, W. Lin and 6 other author(s). ISSCC, page 108-110. IEEE, (2018)A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.J. Hudner, D. Carey, R. Casey, K. Hearne, P. de Abreu Farias Neto, I. Chlis, M. Erett, C. Poon, A. Laraba, H. Zhang and 5 other author(s). VLSI Circuits, page 47-48. IEEE, (2018)A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.M. Raj, C. Xie, A. Bekele, A. Chou, W. Zhang, Y. Cao, J. Kim, N. Narang, H. Zhao, Y. Wang and 7 other author(s). ISSCC, page 204-205. IEEE, (2023)

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Disambiguation of "Frans, Yohan"

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URL
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A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

Please choose a person to relate this publication to

Yohan Shim

Yohan Seo

Yohan Lejosne

Fekadu Yohannes

Indra Yohannes

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Frans, Yohan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

Please choose a person to relate this publication to

Yohan Shim

Yohan Seo

Yohan Lejosne

Fekadu Yohannes

Indra Yohannes

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.