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A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

B. Leibowitz, J. Kizer, H. Lee, F. Chen, A. Ho, M. Jeeradit, A. Bansal, T. Greer, S. Li, R. Farjad-Rad, W. Stonecypher, Y. Frans, B. Daly, F. Heaton, B. Garlepp, C. Werner, N. Nguyen, V. Stojanovic, and J. Zerbe. ISSCC, page 228-599. IEEE, (2007)

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Jared Sonnicksen

Jared Wicks

Jared Miller

Jared Dulmage

Jared Leo

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Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.E. Chen, J. Ren, B. Leibowitz, H. Lee, Q. Lin, K. Oh, F. Lambrecht, V. Stojanovic, J. Zerbe, and C. Yang. IEEE J. Solid State Circuits, 43 (9): 2144-2156 (2008)A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.D. Dunwell, A. Carusone, J. Zerbe, B. Leibowitz, B. Daly, and J. Eble. CICC, page 1-4. IEEE, (2012)Equalizer design and performance trade-offs in ADC-based serial links.J. Kim, J. Ren, B. Leibowitz, P. Satarzadeh, A. Abbasfar, and J. Zerbe. CICC, page 1-8. IEEE, (2010)A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.M. Hossain, K. Kaviani, B. Daly, M. Shirasgaonkar, W. Dettloff, T. Stone, K. Prabhu, B. Tsang, J. Eble, and J. Zerbe. CICC, page 1-4. IEEE, (2012)A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.K. Kaviani, M. Hossain, M. Nazari, F. Heaton, J. Ren, and J. Zerbe. CICC, page 1-4. IEEE, (2012)A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM.T. Lee, K. Donnelly, J. Ho, J. Zerbe, M. Johnson, and T. Ishikawa. IEEE J. Solid State Circuits, 29 (12): 1491-1496 (December 1994)Improving CDR Performance via Estimation.H. Lee, A. Bansal, Y. Frans, J. Zerbe, S. Sidiropoulos, and M. Horowitz. ISSCC, page 1296-1303. IEEE, (2006)Power-efficient I/O design considerations for high-bandwidth applications.J. Eble, S. Best, B. Leibowitz, L. Luo, R. Palmer, J. Wilson, J. Zerbe, A. Amirkhany, and N. Nguyen. CICC, page 1-8. IEEE, (2011)Transition-limiting codes for 4-PAM signaling in high speed serial links.A. Bessios, W. Stonecypher, A. Agarwal, and J. Zerbe. GLOBECOM, page 3747-3751. IEEE, (2003)A 40-Gb/s serial link transceiver in 28-nm CMOS technology.E. Chen, M. Hossain, B. Leibowitz, R. Navid, J. Ren, C. Chou, B. Daly, M. Aleksic, B. Su, S. Li and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)

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Disambiguation of "Zerbe, Jared"

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A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

Please choose a person to relate this publication to

Jared Sonnicksen

Jared Wicks

Jared Miller

Jared Dulmage

Jared Leo

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zerbe, Jared"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.

Please choose a person to relate this publication to

Jared Sonnicksen

Jared Wicks

Jared Miller

Jared Dulmage

Jared Leo

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
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APA
Chicago
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A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.