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Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling., , , , и . A-SSCC, стр. 1-3. IEEE, (2021)A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS., , , , , , , , , и 11 other автор(ы). A-SSCC, стр. 5-8. IEEE, (2018)Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application., , , и . VLSI, том 162 из IFIP Conference Proceedings, стр. 1-10. Kluwer, (1999)A 22 nm 15-Core Enterprise Xeon® Processor Family., , , , , , , , , и . IEEE J. Solid State Circuits, 50 (1): 35-48 (2015)5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family., , , , , , , , , и . ISSCC, стр. 102-103. IEEE, (2014)Quadruped Robot Hopping on Two Legs., , , и . IROS, стр. 7448-7455. IEEE, (2021)Interconnect in the Era of 3DIC., , , и . CICC, стр. 1-5. IEEE, (2022)A Lower Power CMOS Micromixer for GHz Wireless Applications., , , и . VLSI, том 162 из IFIP Conference Proceedings, стр. 35-46. Kluwer, (1999)Clock generation for a 32nm server processor with scalable cores., , , , и . ISSCC, стр. 82-83. IEEE, (2011)