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Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling.

, , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling., , , , and . A-SSCC, page 1-3. IEEE, (2021)A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS., , , , , , , , , and 11 other author(s). A-SSCC, page 5-8. IEEE, (2018)A Lower Power CMOS Micromixer for GHz Wireless Applications., , , and . VLSI, volume 162 of IFIP Conference Proceedings, page 35-46. Kluwer, (1999)Quadruped Robot Hopping on Two Legs., , , and . IROS, page 7448-7455. IEEE, (2021)Interconnect in the Era of 3DIC., , , and . CICC, page 1-5. IEEE, (2022)Clock generation for a 32nm server processor with scalable cores., , , , and . ISSCC, page 82-83. IEEE, (2011)5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family., , , , , , , , , and . ISSCC, page 102-103. IEEE, (2014)A 22 nm 15-Core Enterprise Xeon® Processor Family., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 35-48 (2015)Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application., , , and . VLSI, volume 162 of IFIP Conference Proceedings, page 1-10. Kluwer, (1999)