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Disambiguation of "Seo, Min-Jae"

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A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section.

, , , , , , , , , , and . EMBC, page 4012-4015. IEEE, (2020)

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Min-Soon Seo

Jae-Min Kim

Jae-Min Lee

Jae-Min Lee

Min-Jae Kwon

 

Other publications of authors with the same name

A Hardware-efficient Rate Encoding Hardware with Latch-based TRNG., , and . ICEIC, page 1-4. IEEE, (2024)A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section., , , , , , , , , and 1 other author(s). EMBC, page 4012-4015. IEEE, (2020)A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC., , , , , , and . IEEE J. Solid State Circuits, 59 (8): 2481-2491 (August 2024)An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC., , , , , and . CICC, page 1-2. IEEE, (2023)A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC., , , and . VLSI Circuits, page 72-. IEEE, (2019)A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2024)A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling., , , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 1139-1148 (2018)A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (11): 3617-3627 (2018)A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability., , , , , , , , , and . A-SSCC, page 189-192. IEEE, (2019)A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC., , , , , , , , and . IEEE J. Solid State Circuits, 51 (8): 1826-1839 (2016)