Author of the publication

Low Static Powered Asynchronous Data Transfer for GALS System.

, and . IEICE Trans. Inf. Syst., 91-D (4): 1189-1192 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Appropriate Synchronization Time Allocation for Distributed Heterogeneous Parallel Computing Systems., , and . KSII Trans. Internet Inf. Syst., 13 (11): 5446-5463 (2019)Verification of Interconnect RTL Code for Memory-Centric Computing using UVM., , and . ICEIC, page 1-4. IEEE, (2021)PCIe Bridge Hardware for Gen-Z Memory System., , , and . ICEIC, page 1-3. IEEE, (2021)472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device., , , and . IEICE Electron. Express, 8 (9): 676-683 (2011)Low Static Powered Asynchronous Data Transfer for GALS System., and . IEICE Trans. Inf. Syst., 91-D (4): 1189-1192 (2008)Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (5): 1379-1383 (2005)A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic., and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 691-700. Springer, (2004)Design of a clockless MSP430 core using mixed asynchronous design flow., , , , and . IEICE Electron. Express, 14 (8): 20170162 (2017)Functional unit duplication for reducing dynamic power., , , , , and . IEICE Electron. Express, 7 (2): 98-104 (2010)Fine-grained power gating of datapath using FSM., , , and . NESEA, page 1-5. IEEE Computer Society, (2011)