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Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors., , , и . J. Supercomput., 65 (2): 771-796 (2013)Towards Enhanced System Efficiency while Mitigating Row Hammer., , и . ACM Trans. Archit. Code Optim., 18 (4): 40:1-40:26 (2021)Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor., и . ISVLSI, стр. 182-187. IEEE Computer Society, (2017)Dynamic Associativity Management Using Fellow Sets., и . ISED, стр. 133-137. IEEE Computer Society, (2013)Power aware cache miss reduction by energy efficient victim retention., , и . VDAT, стр. 1-6. IEEE Computer Society, (2015)Static energy reduction by performance linked cache capacity management in tiled CMPs., , и . SAC, стр. 1913-1918. ACM, (2015)Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines., , , и . J. Parallel Distributed Comput., (2019)An Approach for Multicast Routing in Networks-on-Chip., , и . ICIT, стр. 299-304. IEEE, (2014)Towards a Better Cache Utilization Using Controlled Cache Partitioning., , и . DASC, стр. 179-186. IEEE Computer Society, (2013)Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks., , и . IPDPS Workshops, стр. 444-453. IEEE Computer Society, (2015)