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Disambiguation of "De, Vivek K."

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A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 46 (1): 194-208 (2011)

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Vivek K Velamuri

Christian K de Lamboy

Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

 

Other publications of authors with the same name

Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance., , , , , , , and . ISSCC, page 402-403. IEEE, (2008)All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control., , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 2017-2025 (2011)A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 194-208 (2011)An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS., , , , , , and . ISSCC, page 1-3. IEEE, (2022)Short channel models and scaling limits of SOI and bulk MOSFETs., , , and . IEEE J. Solid State Circuits, 29 (2): 122-125 (February 1994)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance., , , , and . IEEE J. Solid State Circuits, 48 (4): 907-916 (2013)Adaptive and Resilient Circuits for Dynamic Variation Tolerance., , , , and . IEEE Des. Test, 30 (6): 8-17 (2013)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)A 22nm dynamically adaptive clock distribution for voltage droop tolerance., , , , and . VLSIC, page 94-95. IEEE, (2012)