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Disambiguation of "Bostanci, F. Nisa"

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MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations.

, , , , , , , and . ACM Trans. Archit. Code Optim., 19 (2): 26:1-26:29 (2022)

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Özlem Bostanci

Öznur Bostanci

Emine Bostanci

Sevgi Bostanci

Yasmin Nisar

 

Other publications of authors with the same name

Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis., , , , , , , , , and . HPCA, page 280-296. IEEE, (2024)Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources., , , , , , , and . CoRR, (2023)DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators., , , , , , , and . HPCA, page 1141-1155. IEEE, (2022)MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing., , , , , , and . HPCA, page 186-203. IEEE, (2024)Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator., , , , , and . IEEE Comput. Archit. Lett., 23 (1): 112-116 (January 2024)MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations., , , , , , , and . ACM Trans. Archit. Code Optim., 19 (2): 26:1-26:29 (2022)Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations., , , , , , , , and . CoRR, (2024)CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost., , , , , , , and . HPCA, page 593-612. IEEE, (2024)Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings., , , , , , , , , and 1 other author(s). MICRO, page 1196-1212. ACM, (2023)Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis., , , , , , , , , and 1 other author(s). DSN, page 99-114. IEEE, (2024)