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Disambiguation of "Kim, Jae-Joon"

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A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (3): 349-357 (2005)

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Joon-Young Kim

Nam-Joon Kim

Man Joon Kim

Joon-Soon Kim

Hyun-Joon Kim

 

Other publications of authors with the same name

A forward body-biased low-leakage SRAM cache: device and architecture considerations., , , and . ISLPED, page 6-9. ACM, (2003)A CMOS single-chip wireless solution with an adaptive purity-control scheme against ISM-band interferences., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (4): 269-273 (2006)PVT-aware leakage reduction for on-die caches with improved read stability., , , and . IEEE J. Solid State Circuits, 41 (1): 170-178 (2006)BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks., , , , , , and . IEEE J. Solid State Circuits, 57 (6): 1924-1935 (2022)Environment-Adaptable Edge-Computing Gas-Sensor Device With Analog-Assisted Continual Learning Scheme., , , , , , , and . IEEE Trans. Ind. Electron., 70 (10): 10720-10729 (October 2023)A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies., and . IEEE Trans. Very Large Scale Integr. Syst., 14 (5): 549-552 (2006)Magnetic Induction Tomography Using Multi-Channel Phase-Domain Transceiver for Structural Health Monitoring., , , , , and . IEEE Trans. Instrum. Meas., (2022)A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS., , , and . ISSCC, page 388-389. IEEE, (2008)Highly improved SNR differential sensing method using parallel operation signaling for touch screen application., , , and . A-SSCC, page 157-160. IEEE, (2014)1/f Noise in Synaptic Ferroelectric Tunnel Junction: Impact on Convolutional Neural Network., , , , , , , , and . Adv. Intell. Syst., (June 2023)