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Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs.

, , , and . ISPD, page 47-54. ACM, (2014)

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Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options., , , , and . DAC, page 1189-1194. IEEE, (2021)Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs., and . DAC, page 925-930. IEEE, (2021)RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs., , , , , , , , , and 1 other author(s). DAC, page 101. ACM, (2019)Exploiting die-to-die thermal coupling in 3D IC placement., , and . DAC, page 741-746. ACM, (2012)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM., , , , , , and . DAC, page 91:1-91:6. ACM, (2015)Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects., and . ISQED, page 228-335. IEEE, (2012)Signal integrity analysis and optimization for 3D ICs., , and . ISQED, page 42-49. IEEE, (2011)A generic reconfigurable array specification and programming environment (GRASPER)., , , and . ECCTD, page 619-622. IEEE, (2009)A unified methodology for power supply noise reduction in modern microarchitecture design., , , and . ASP-DAC, page 611-616. IEEE, (2008)Statistical Bellman-Ford algorithm with an application to retiming., , and . ASP-DAC, page 959-964. IEEE, (2006)