Author of the publication

An efficient solution to the storage correspondence problem for large sequential circuits.

, , and . ASP-DAC, page 181-186. ACM, (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise., , and . NATW, page 61-64. IEEE, (2014)Maximizing crosstalk-induced slowdown during path delay test., and . ICCD, page 159-166. IEEE Computer Society, (2012)Challenges in Delay Testing of Integrated Circuits.. DFT, page 81-82. IEEE Computer Society, (2009)Mixed structural-functional path delay test generation and compaction., , , and . DFTS, page 7-12. IEEE Computer Society, (2013)Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages., and . ITC, page 767-775. IEEE Computer Society, (1996)IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays., , and . IEEE Trans. Computers, 47 (10): 1136-1152 (1998)Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation., , and . VLSID, page 50-55. IEEE Computer Society, (2014)A practical built-in current sensor for I_DDQ testing., , and . ITC, page 405-414. IEEE Computer Society, (2001)Improved wafer-level spatial analysis for I_DDQ limit setting., and . ITC, page 82-91. IEEE Computer Society, (2001)Levelized low cost delay test compaction considering IR-drop induced power supply noise., , , and . VTS, page 52-57. IEEE Computer Society, (2011)