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Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise.

, , and . NATW, page 61-64. IEEE, (2014)

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Bridging Fault Detection in FPGA Interconnects Using IDDQ., , and . FPGA, page 95-104. ACM, (1998)VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 5 (4): 541-556 (1986)The CDB/HCDB semiconductor wafer representation server., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (2): 283-295 (1993)A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator., , and . DAC, page 579-584. ACM, (1991)Optimal voltage testing for physically-based faults., and . VTS, page 344-353. IEEE Computer Society, (1996)Improvement of SRAM-based failure analysis using calibrated Iddq testing., and . VTS, page 130-137. IEEE Computer Society, (1996)Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits., and . VTS, page 70-79. IEEE Computer Society, (1999)Power Supply Noise in Delay Testing., , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)Accurate Fault Modeling and Fault Simulation of Resistive Bridges., and . DFT, page 102-107. IEEE Computer Society, (1998)Accurate yield estimation of circuits with redundancy., , and . DFT, page 155-163. IEEE Computer Society, (1995)