( en | de | ru )

 

Disambiguation of "Tanaka, Tetsu"

Author of the publication

copydeleteadd this publication to your clipboard
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration.

, , , , , , , , and . 3DIC, page 1-5. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tetsu Kudo

Masao Tanaka

Masafumi Tanaka

Shu Tanaka

Shin Tanaka

 

Other publications of authors with the same name

Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University., , , , and . 3DIC, page FS2.1-FS2.5. IEEE, (2015)Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology., , , , , and . 3DIC, page 1-4. IEEE, (2016)A study on multipath propagation characteristics for RAKE receiving technique.. PIMRC, page 711-714. (1994)Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last., , , , , , , , and . 3DIC, page 1-4. IEEE, (2023)Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration., , , , , , , , and . Micromachines, 7 (10): 184 (2016)Investigation of the Underfill with Negative-Thermal-Expansion Material to Suppress Mechanical Stress in 3D Integration System., , and . 3DIC, page 1-4. IEEE, (2019)Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation., , , , , , , and . 3DIC, page 1-4. IEEE, (2019)Development of a CDS Circuit for 3-D Stacked Neural Network Chip using CMOS Analog Signal Processing., , , , , and . 3DIC, page 1-4. IEEE, (2019)Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC., , , , , , , and . 3DIC, page TS8.26.1-TS8.26.4. IEEE, (2015)A parallel ADC for high-speed CMOS image processing system with 3D structure., , , , , , and . 3DIC, page 1-4. IEEE, (2009)