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Characterization of sequential cells for constraint sensitivities.

, , , , and . ISQED, page 74-79. IEEE Computer Society, (2009)

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Optimal placement of power-supply pads and pins., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (1): 144-154 (2006)Impact of stress-induced backflow on full-chip electromigration risk assessment., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1038-1046 (2006)Coupling Noise., , and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)Guest Editorial: Special Issue on VLSI Design and Embedded Systems., and . Int. J. Parallel Program., 38 (3-4): 183-184 (2010)Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing., , , , , , and . DAC, page 436-441. ACM Press, (1999)Stochastic Power Grid Analysis Considering Process Variations, , , and . CoRR, (2007)Worst case clock skew under power supply variations., , , , , , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 22-28. ACM, (2002)On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise., , , , , , , and . DAC, page 162-167. IEEE, (2007)A stochastic approach To power grid analysis., , , , and . DAC, page 171-176. ACM, (2004)Signal integrity management in an SoC physical design flow., , , and . ISPD, page 39-46. ACM, (2003)