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Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (3): 1017-1030 (2019)Improved Implementation of CRL and SCRL Gates for Ultra Low Power., , and . ARTCom, page 123-125. IEEE Computer Society, (2009)22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors., , , , , , , , , and 3 other author(s). ISSCC, page 390-392. IEEE, (2024)A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers., , , , and . ARTCom, page 115-117. IEEE Computer Society, (2009)A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET., , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Continuous-time hybrid computation with programmable nonlinearities., , , , , , , and . ESSCIRC, page 279-282. IEEE, (2015)A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs., , , , , , , , , and 1 other author(s). CICC, page 1-2. IEEE, (2023)16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter., , , , , , , , , and 5 other author(s). ISSCC, page 260-262. IEEE, (2020)A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET., , , , , , , and . IEEE J. Solid State Circuits, 59 (4): 1158-1170 (April 2024)