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Disambiguation of "Kelefouras, Vasilios I."

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Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs.

, , , , , and . Journal of Circuits, Systems, and Computers, 25 (4): 1650032:1-1650032:26 (2016)

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Vasilios Trakas

Vasilios Katos

Vasilios Gemenetzis

Vasilios Darlagiannis

Vasilios Zorkadis

 

Other publications of authors with the same name

Workflow Simulation Aware and Multi-threading Effective Task Scheduling for Heterogeneous Computing., and . HiPC, page 215-224. IEEE, (2018)XANDAR: A holistic Cybersecurity Engineering Process for Safety-critical and Cyber-physical Systems., , , , , , , , , and 16 other author(s). VTC Spring, page 1-5. IEEE, (2022)Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management., , and . ISVLSI, page 477-482. IEEE Computer Society, (2017)XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems., , , , , , , , , and 16 other author(s). DATE, page 1-5. IEEE, (2022)A methodology for speeding up matrix vector multiplication for single/multi-core architectures., , , and . J. Supercomput., 71 (7): 2644-2667 (2015)Evaluation of Language Runtimes in Open-source Serverless Platforms., , and . CLOSER, page 123-132. SCITEPRESS, (2022)Towards Highly Compressed CNN Models for Human Activity Recognition in Wearable Devices., , , , and . SPA, page 83-88. IEEE, (2023)A methodology for efficient code optimizations and memory management., and . CF, page 105-112. ACM, (2018)An Analytical Model for Loop Tiling Transformation., , , and . SAMOS, volume 13227 of Lecture Notes in Computer Science, page 95-107. Springer, (2021)A Methodology for Efficient Tile Size Selection for Affine Loop Kernels., , , and . Int. J. Parallel Program., 50 (3-4): 405-432 (2022)