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Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs.

, , , , , and . Journal of Circuits, Systems, and Computers, 25 (4): 1650032:1-1650032:26 (2016)

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A High Performance Bitplane Encoder for the CCSDS 122.0-B-1 Compression Standard., and . TSP, page 1-7. IEEE, (2018)Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path., , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 868-873. Springer, (2004)The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 221-233 (2009)A Framework for Data Partitioning for C++ Data-Intensive Applications., , , , , , and . Des. Autom. Embed. Syst., 9 (2): 101-121 (2004)A hybrid approach for mapping and scheduling on heterogeneous multicore systems., , , and . SAMOS, page 360-365. IEEE, (2016)A parallel luma-chroma filtering architecture for H.264/AVC deblocking filter., and . ICCE-Berlin, page 273-276. IEEE, (2015)High-performance FPGA implementations of volterra DFEs for optical fiber systems., , and . ReConFig, page 1-8. IEEE, (2014)A novel high-speed counter with counting rate independent of the counter's length., , , and . ICECS, page 1164-1167. IEEE, (2003)Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers., , , , and . J. Low Power Electron., 2 (3): 356-364 (2006)Behavioral-level event-driven power management for DECT digital receivers., , and . Microelectron. J., 36 (2): 163-172 (2005)