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647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA.

, , , , и . ESSCIRC, стр. 156-159. IEEE, (2009)

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Sam Devlin

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Lorettann Devlin-Gascard

 

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Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging., , , и . DFT, стр. 3. IEEE Computer Society, (2010)A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS., , и . ASP-DAC, стр. 75-76. IEEE, (2011)Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes., , и . ASYNC, стр. 150-157. IEEE Computer Society, (2012)A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment., , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1319-1328 (2010)647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA., , , , и . ESSCIRC, стр. 156-159. IEEE, (2009)Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system., , и . ICECS, стр. 53-56. IEEE, (2011)Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA., , и . ISLPED, стр. 3-8. IEEE/ACM, (2011)A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation., , и . IEEE J. Solid State Circuits, 46 (11): 2500-2513 (2011)Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation., , и . COOL Chips, стр. 1-3. IEEE Computer Society, (2012)