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A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop., , , , , and . A-SSCC, page 1-3. IEEE, (2021)Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture., , , , , , , , , and 7 other author(s). MICRO, page 14-27. ACM, (2019)8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring., , , , , , , and . ISSCC, page 156-157. IEEE, (2016)Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET., , , , , , and . CICC, page 1-4. IEEE, (2019)6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links., , , , , , , , , and 1 other author(s). ISSCC, page 126-128. IEEE, (2020)A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET., , , , , , , , , and . ASYNC, page 27-35. IEEE, (2019)A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (4): 920-932 (2020)A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm., , , , , , , , , and 7 other author(s). VLSI Circuits, page 300-. IEEE, (2019)An Engineering Environment for Hardware/Software Co-Simulation., , and . DAC, page 129-134. IEEE Computer Society Press, (1992)