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Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits., , , and . ISCAS, page 428-431. IEEE, (2012)Correlated jitter sampling for jitter cancellation in pipelined TDC., , , and . ISCAS, page 810-813. IEEE, (2012)Ring amplifiers for switched-capacitor circuits., , , , , and . ISSCC, page 460-462. IEEE, (2012)Analysis of back-end flash in a 1.5b/stage pipelined ADC., , and . ISCAS, page 2247-2250. IEEE, (2013)An improved algorithmic ADC clocking scheme., , and . ISCAS (1), page 589-592. IEEE, (2004)A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 269-275 (2004)Continuous-time filter design optimized for reduced die area., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (3): 105-110 (2004)Domino-Logic-Based ADC for Digital Synthesis., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (11): 744-747 (2011)Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC., , , , , , and . IEEE J. Solid State Circuits, 45 (4): 719-730 (2010)A Power Efficient SAR Algorithm for High Resolution ADCs., , , , , , and . ISCAS, page 1-5. IEEE, (2018)