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A 10b Ternary SAR ADC with decision time quantization based redundancy., , , , and . A-SSCC, page 65-68. IEEE, (2011)A 10-b Ternary SAR ADC With Quantization Time Information Utilization., , , , and . IEEE J. Solid State Circuits, 47 (11): 2604-2613 (2012)Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling., , , , and . IEEE J. Solid State Circuits, 49 (8): 1715-1724 (2014)The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (8): 1733-1742 (2012)Analysis of back-end flash in a 1.5b/stage pipelined ADC., , and . ISCAS, page 2247-2250. IEEE, (2013)A 71dB dynamic range third-order ΔΣ TDC using charge-pump., , , and . VLSIC, page 168-169. IEEE, (2012)An interstage correlated double sampling technique for switched-capacitor gain stages., , , , and . ISCAS, page 1252-1255. IEEE, (2010)A ΔΣ ADC using an LSB-first SAR quantizer., , , and . ISCAS, page 1638-1641. IEEE, (2015)Blind background calibration of harmonic distortion based on selective sampling., , , , and . CICC, page 1-4. IEEE, (2013)Parallel gain enhancement technique for switched-capacitor circuits., , , , , , and . CICC, page 1-4. IEEE, (2013)