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Disambiguation of "Mercha, Abdelkarim"

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Modeling FinFET metal gate stack resistance for 14nm node and beyond.

, , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

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Abdelkarim Habib

Abdelkarim Omar

Abdelkarim Mouhssine

Abdelkarim Kerbaa

Abdelkarim Belhoula

 

Other publications of authors with the same name

Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges., , , , and . CICC, page 679-686. IEEE, (2006)Analysis of microbump induced stress effects in 3D stacked IC technologies., , , , , , , , , and 9 other author(s). 3DIC, page 1-5. IEEE, (2011)Holisitic device exploration for 7nm node., , , , , , , , , and 5 other author(s). CICC, page 1-5. IEEE, (2015)Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Technology and architecture for deep submicron RF CMOS technology.. SBCCI, page 4. ACM, (2005)A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 40 (7): 1434-1442 (2005)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , and . ESSDERC, page 159-162. IEEE, (2013)Low-cost feedback-enabled LNAs in 45nm CMOS., , , , and . ESSCIRC, page 100-103. IEEE, (2009)A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS., , , , , , , , , and . ESSCIRC, page 291-294. IEEE, (2004)Identifying the Bottlenecks to the RF Performance of FinFETs., , , , , , and . VLSI Design, page 111-116. IEEE Computer Society, (2010)