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Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel.

, , , , and . Tiny Papers @ ICLR, OpenReview.net, (2024)

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Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (11): 1817-1830 (2017)Architecture and synthesis for multi-cycle on-chip communication., , , , and . CODES+ISSS, page 77-78. ACM, (2003)High-level synthesis with timing-sensitive information flow enforcement., , , and . ICCAD, page 88. ACM, (2018)An efficient and versatile scheduling algorithm based on SDC formulation., and . DAC, page 433-438. ACM, (2006)A reconfigurable analog substrate for highly efficient maximum flow computation., and . DAC, page 17:1-17:6. ACM, (2015)Application-specific instruction generation for configurable processor architectures., , , and . FPGA, page 183-189. ACM, (2004)LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure., , , , and . FCCM, page 74-77. IEEE, (2019)Mapping-Aware Constrained Scheduling for LUT-Based FPGAs., , , and . FPGA, page 190-199. ACM, (2015)Special Session: Machine Learning for Embedded System Design., , , , , , , , , and 1 other author(s). CODES+ISSS, page 28-37. IEEE, (2023)Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks., , , , , and . ASP-DAC, page 152-157. ACM, (2021)