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Disambiguation of "Inoue, Kazuki"

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Evaluation of fault tolerant technique based on homogeneous FPGA architecture.

, , , , , and . VLSI-SoC, page 225-230. IEEE, (2012)

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Heide Inoue

Tomoyuki Inoue

Norman Inoue

Hiroko Inoue

Kenji Inoue

 

Other publications of authors with the same name

Understanding Fake Faces., , , , , and . ECCV Workshops (3), volume 11131 of Lecture Notes in Computer Science, page 566-576. Springer, (2018)A Novel Local Interconnect Architecture for Variable Grain Logic Cell., , , and . ARC, volume 5453 of Lecture Notes in Computer Science, page 97-109. Springer, (2009)An easily testable routing architecture of FPGA., , , and . VLSI-SoC, page 106-109. IEEE, (2011)Evaluation of human distress by one's walking speed - toward development of early warning system for marine pilots' condition., , , and . SoSE, page 72-76. IEEE, (2011)Defect-robust FPGA architectures for intellectual property cores in system LSI., , , , , and . FPL, page 1-7. IEEE, (2013)Fault detection and avoidance of FPGA in various granularities., , , , , and . FPL, page 539-542. IEEE, (2012)A novel physical defects recovery technique for FPGA-IP cores., , , , , and . ReConFig, page 1-7. IEEE, (2012)A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)., , , , , and . FPGA, page 271. ACM, (2013)An Easily Testable Routing Architecture and Efficient Test Technique., , , , and . FPL, page 291-294. IEEE Computer Society, (2011)Evaluation of fault tolerant technique based on homogeneous FPGA architecture., , , , , and . VLSI-SoC, page 225-230. IEEE, (2012)