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Disambiguation of "Nose, Koichi"

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20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications.

, , , , , , , and . ISSCC, page 364-366. IEEE, (2024)

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Koichi Matsumoto

Koichi Koshi

Koichi Morikawa

Dorit Nose

Karl Nosek

 

Other publications of authors with the same name

A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme., , , , , , and . VLSIC, page 16-17. IEEE, (2012)Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology., and . ISLPED, page 24-29. ACM, (2002)Design methodology and optimization strategy for dual-VTH scheme using commercially available tools., , and . ISLPED, page 283-286. ACM, (2001)A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2., , , and . VLSI Circuits, page 248-. IEEE, (2019)20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications., , , , , , , and . ISSCC, page 364-366. IEEE, (2024)Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)., , and . ISLPED, page 228-230. ACM, (2000)Optimization of VDD and VTH for low-power and high speed applications., and . ASP-DAC, page 469-474. ACM, (2000)Analysis and future trend of short-circuit power., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (9): 1023-1030 (2000)Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops., , and . ISSCC, page 402-611. IEEE, (2007)Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics., , , , , , , , , and 2 other author(s). ISSCC, page 1686-1695. IEEE, (2006)