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Disambiguation of "Juan-Chico, Jorge"

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Static Power Consumption in CMOS Gates Using Independent Bodies.

, , , , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)

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Jorge Juan Robles

Sydney Chicouri

Jean-Jérôme Chico-Kaleu Muyemba

Hsiao-Mei Juan

Manuel Chico Cano

 

Other publications of authors with the same name

Using the complement of the cosine to compute trigonometric functions., , , , , , and . EURASIP J. Adv. Signal Process., 2020 (1): 1-21 (2020)Inertial and degradation delay model for CMOS logic gates., , , , and . ISCAS, page 459-462. IEEE, (2000)HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model., , , , and . DATE, page 467-471. IEEE Computer Society, (2001)Degradation Delay Model Extension to CMOS Gates., , , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 149-158. Springer, (2000)Internode: Internal Node Logic Computational Model., , , , , and . Annual Simulation Symposium, page 241-248. IEEE Computer Society, (2003)Improving the Performance of Static CMOS Gates by Using Independent Bodies., , , , , , and . J. Low Power Electron., 3 (1): 70-77 (2007)Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits., , , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 316-326. Springer, (2000)Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits., , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 501-510. Springer, (2003)Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)., , , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 477-486. Springer, (2002)Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level., , , , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 353-362. Springer, (2002)