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Increasing Cellular Network Energy Efficiency for Railway Corridors., , and . DATE, page 1103-1106. IEEE, (2022)On self-interference suppression methods for low-complexity full-duplex MIMO., , , and . ACSSC, page 992-997. IEEE, (2013)LoRa Symbol Error Rate Under Non-Aligned Interference., , , and . ACSSC, page 1957-1961. IEEE, (2019)On the Implementation Complexity of Digital Full-Duplex Self-Interference Cancellation., , and . ACSSC, page 969-973. IEEE, (2020)Full-duplex communications for wireless links with asymmetric capacity requirements., , , and . ACSSC, page 1682-1686. IEEE, (2017)Efficient vlsi implementation of reduced-state sequence estimation for wireless communications., , , and . ICASSP, page 2528-2532. IEEE, (2013)Coded LoRa Frame Error Rate Analysis., , and . ICC, page 1-6. IEEE, (2020)Area- and throughput-optimized VLSI architecture of sphere decoding., , , and . VLSI-SoC, page 189-194. IEEE, (2010)DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment., , , , , and . ESSCIRC, page 261-264. IEEE, (2016)An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications., , , , , and . ESSCIRC, page 308-311. IEEE, (2017)