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Disambiguation of "Valero, Mateo"

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MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications.

, , and . SC, page 15. ACM, (1999)

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Ana Maria Mateo Rosell

Carlos Mateo Balmelli

Mateo Hermel

Alejandro Valero

Silvia Valero

 

Other publications of authors with the same name

Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Memory Access Synchronization in Vector Multiprocessors., , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 414-425. Springer, (1994)Parallel Computer Architecture., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 537-538. Springer, (2000)Initial Evaluation of Multimedia Extensions on VLIW Architectures., and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 403-412. Springer, (2004)Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units., , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 88-97. Springer, (2004)The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment., , , , , , and . Conf. Computing Frontiers, page 67-78. ACM, (2008)Hardware Transactional Memory with Operating System Support, HTMOS., , , and . Euro-Par Workshops, volume 4854 of Lecture Notes in Computer Science, page 8-17. Springer, (2007)Overlapping communication and computation by using a hybrid MPI/SMPSs approach., , , and . ICS, page 5-16. ACM, (2010)