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Low leakage circuit design for FPGAs., , and . CICC, page 715-718. IEEE, (2004)A Multi-Context Pipelined Array for Embedded Systems., , , , , and . FPL, page 1-8. IEEE, (2006)Decoder-Based Multi-Context Interconnect Architecture., , , , and . ISVLSI, page 231-233. IEEE Computer Society, (2003)3D capacitive transmission of analog signals with automatic compensation of the voltage attenuation., , , , , , , and . ESSCIRC, page 116-119. IEEE, (2009)3D Capacitive Interconnections for High Speed Interchip Communication., , , , , , , , and . CICC, page 1-8. IEEE, (2007)Combining low-leakage techniques for FPGA routing design., , and . FPGA, page 208-214. ACM, (2005)3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities., , , , , , , and . ISSCC, page 356-608. IEEE, (2007)A dynamically adaptive DSP for heterogeneous reconfigurable platforms., , , , , , , , and . DATE, page 9-14. EDA Consortium, San Jose, CA, USA, (2007)Compact Buffered Routing Architecture., , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 179-188. Springer, (2004)Low leakage design of LUT-based FPGAs., , , , and . ESSCIRC, page 153-156. IEEE, (2005)