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Disambiguation of "Soumyanath, Krishnamurthy"

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A 90-nm MOS-only 3-11GHz transmitter for UWB.

, , , and . CICC, page 165-168. IEEE, (2005)

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Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Vittala Naranappa Krishnamurthy

 

Other publications of authors with the same name

Desensitized design of MOS low noise amplifiers by Rn minimization., , , , and . ICECS, page 619-622. IEEE, (2004)A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS., , , , and . CICC, page 1-4. IEEE, (2009)A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 48 (1): 91-103 (2013)A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS., , , , and . ESSCIRC, page 535-538. IEEE, (2005)A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS., , and . ESSCIRC, page 352-355. IEEE, (2007)Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends., , , , , and . IEEE J. Solid State Circuits, 36 (11): 1636-1646 (2001)A sub-130-nm conditional keeper technique., , , and . IEEE J. Solid State Circuits, 37 (5): 633-638 (2002)A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity., , , and . IEEE J. Solid State Circuits, 40 (12): 2515-2524 (2005)A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process., , , , and . IEEE J. Solid State Circuits, 44 (12): 3621-3630 (2009)A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS., , , , and . ESSCIRC, page 202-205. IEEE, (2008)