( en | de | ru )

 

Disambiguation of "Kawamura, Kazushi"

Author of the publication

copydeleteadd this publication to your clipboard
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning.

, , , , and . FPT, page 1-10. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hiroki Kawamura

Hiroshi Kawamura

Katsutoshi Kawamura

Eisuke Kawamura

Eiko Kawamura

 

Other publications of authors with the same name

Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA., , , , and . ICCE, page 1-2. IEEE, (2024)Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA., , , , , and . ICCE, page 1-2. IEEE, (2024)Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A partial redundant fault-secure high-level synthesis algorithm for RDR architectures., , , and . ISCAS, page 1736-1739. IEEE, (2013)Restricted Random Pruning at Initialization for High Compression Range., , , , , , and . Trans. Mach. Learn. Res., (2024)Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension., , , , , , , , , and 2 other author(s). ISSCC, page 42-43. IEEE, (2023)FPGA-based Heterogeneous Solver for Three-Dimensional Routing., , , , , and . ASP-DAC, page 11-12. IEEE, (2020)Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket., , , , , , , , and . CoRR, (2024)A loop structure optimization targeting high-level synthesis of fast number theoretic transform., , and . ISQED, page 106-111. IEEE, (2018)A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs., , , , and . APCCAS, page 244-247. IEEE, (2014)