Author of the publication

Bubble Razor: An architecture-independent approach to timing-error detection and correction.

, , , , , , and . ISSCC, page 488-490. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter., , , , , , and . ISSCC, page 188-189. IEEE, (2010)Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes., and . ASP-DAC, page 684-689. ACM, (2021)Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores., , , , , , , , , and 5 other author(s). ISSCC, page 190-192. IEEE, (2012)A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold., , , and . VLSIC, page 200-201. IEEE, (2012)Centip3De: A 64-core, 3D stacked, near-threshold system., , , , , , , , , and 5 other author(s). Hot Chips Symposium, page 1-30. IEEE, (2012)Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning., and . DAC, page 1291-1294. IEEE, (2021)Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks., , , , , and . ASYNC, page 75-82. IEEE Computer Society, (2016)Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture., , , , , , , , , and 7 other author(s). MICRO, page 14-27. ACM, (2019)A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme., , , , , and . ISCAS, page 69-72. IEEE, (2011)Early detection of oxide breakdown through in situ degradation sensing., , , , , , and . ISSCC, page 190-191. IEEE, (2010)