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Disambiguation of "Seo, Jae-Sun"

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Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks.

, , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 34:1-34:22 (2022)

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Sun-Aea Seo

Sun-Jae Lee

Sun-Jae Song

Jae-Sun Kim

Jae Sun Gross-Lee

 

Other publications of authors with the same name

A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip., , , and . ESSCIRC, page 119-122. IEEE, (2019)Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS., , , , and . ISLPED, page 140-145. IEEE, (2015)Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks., , , , and . VLSI-DAT, page 1-2. IEEE, (2019)A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3843-3853 (2019)FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro., , , , , and . ESSCIRC, page 405-408. IEEE, (2023)A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification., , , , , , , , and . ESSCIRC, page 89-92. IEEE, (2022)Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture., , , , , , , and . ICCAD, page 8:1-8:9. ACM, (2022)XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism., , , and . ACM Great Lakes Symposium on VLSI, page 417-422. ACM, (2019)Low Power and Trusted Machine Learning., , , , and . ACM Great Lakes Symposium on VLSI, page 515. ACM, (2018)Deep Neural Network Training Accelerator Designs in ASIC and FPGA., , , and . ISOCC, page 21-22. IEEE, (2020)