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Disambiguation of "Chakrabarti, Chaitali"

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Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks.

, , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 34:1-34:22 (2022)

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Chaitali Chakrabarti

Subhadip Chakrabarti

Gopa Chakrabarti

Romon Chakrabarti

Sudhir Kumar Chakrabarti

 

Other publications of authors with the same name

Articulation constrained learning with application to speech emotion recognition., , , , and . EURASIP J. Audio Speech Music. Process., (2019)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks., , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 34:1-34:22 (2022)Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs., , , , , and . IEEE Des. Test, 37 (6): 79-87 (2020)Communication and Computation Reduction for Split Learning using Asynchronous Training., , and . SiPS, page 76-81. IEEE, (2021)Data storage time sensitive ECC schemes for MLC NAND Flash memories., , , and . ICASSP, page 2513-2517. IEEE, (2013)Improving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration., , , , , , and . ISCAS, page 375-379. IEEE, (2022)Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity., , , , and . INTERSPEECH, page 21-25. ISCA, (2020)A low power scheduling scheme with resources operating at multiple voltages., and . IEEE Trans. Very Large Scale Integr. Syst., 10 (1): 6-14 (2002)VLSI architectures for recursive median filters.. ICASSP (1), page 413-416. IEEE Computer Society, (1993)